Chip design software maker Cadence Design Systems announced a joint
development agreement with IBM to create intellectual property
(IP). The companies say this technology will help customers deliver
leading-edge designs while reducing the risk and time associated
with integrating complex SoC
Designs.
Under the agreement, the companies will develop double data rate
memory PHY cores, memory controllers, and protocols such as PCIe
and Ethernet under 32-nanometer silicon-on-insulator. The
technology will be used in servers, video games and other devices
and will be available through the newly announced Cadence Open
Integration Platform.
“Qualifying and integrating complex IP is a costly and
growing burden for many of our customers,” said Vishal
Kapoor, VP, Product Management of Cadence. “We look forward
to teaming with IBM to relieve some of that burden for engineering
teams as they grapple with SoCs and systems that will only continue
to grow in size and
complexity.”
Commenting on the partnership, Marie Angelopoulos, Director, IBM
Microelectronics said, “The IP we are working on with Cadence
will provide state-of-the-art building blocks that will allow our
customers to build more powerful, higher-bandwidth networking and
communications technology.”
"Disclaimer Note: "InformationWeek India and UBM India do not endorse, and have not verified the views and claims expressed in this vendor Press Release."